VSRVES01 -board is now up and running. Next I try to built RISC-V toolchain and reproduce original image.
Unfortunatelly there is no GIT repo yet, so I have to build it from scratch.
JTAG debugging bus is not implemented:
"There is no JTAG. It would make life more miserable because it works on write register, read memory and so on to debug Linux program. So print debug it is."