Tiny Core Base > Other architectures
Which board to support?
gadget42:
this commentary refers to the Rock-PI 4 from Radxa
https://research.exoticsilicon.com/articles/sbc_bootcamp_2021
Yleisajattelija:
Manual for VSRV:
https://www.vlsi.fi/fileadmin/products/vsrv/vsrv_guide.pdf
Implemented RISC-V flavour:
----------------
The exactflavour of the core is RV32IMSU zicsr zifencei.
----------------
--RV32I = "base integer instruction set" (fixed 32bit)
--M = "Extension for Integer Multiplication and Division" (for FIR-filters?)
--S = "Supervisor mode" (=separate mem ja cmds for root space)
--U = "User mode" (=separate mem and cmds for user space)
--zicsr = "Extension for Control and Status Register (CSR) Istructions (physical mem control?)
--zifencei = "Extension for Istruction-Fetch Fence" (for protected mode caches?).
Memory controller:
-----------------------------
LPDDR2 Interface
LPDDR2 is connected to the Instruction and Data Caches of VSRV1, making it themain RAM memory of the unit. RISC-V cannot be run without LPDDR2.
------------------------------
SD-card is connected to VSDSP6-core bus, not VSRV1RISC-VCORE bus, which may be problem for tc-port.
Those buses are MUX:ed, but mux may prevent boot from SD-card.
UART-boot:
----------------------------------------------
(I think there is bug on document, these two UART boot sections are on wrong sections)
Boot UART
Connected either to pins RV_TX and RV_RX and/or to VSDSP6’s UARTMUX.
Speed is always RVCLKI/12, where RVCLKI is RISC-V’s internal clock.
UARTMUX
UARTMUX connects to VSRV1 boot UART.
-----------------------------------------------
Anyway, UART-boot is GOOD news for tc port....
DSP-core IS real time:
--------------------------
Having all these features gives VSDSP high signal processing power beyond its MHz
figures.
The extremely low latency in serving an interrupt (usually significantly below 10 µs even
in a loaded system) allows for implementing a real-time system with audio latencies from
input to output in the order of less than 5 milliseconds.
-------------------------
Yleisajattelija:
Fresh VSRV -board shell documentation:
https://www.vlsi.fi/fileadmin/products/vsrv/vsrv_vsos_shell.pdf
Tristan RISC-V documentation:
https://www.vlsi.fi/fileadmin/vsriscv/VSRV1/TRISTAN_D2.1_Architecture_Description_and_Design_Specification_VLSI.pdf
https://www.vlsi.fi/fileadmin/vsriscv/VSRV1/TRISTAN_D2.2_Design_and_Implementation_of_RISC-V_Cores_and_Extensions_VLSI.pdf
There is SOC data sheet (pin numbers etc.):
https://www.vlsi.fi/fileadmin/datasheets/vsrves01_ds.pdf
Very pro...
Couple of pins:
Pin 33: Mem mux, jumper maybe?
Pin 43/44 UART RV_RX/TX (RV = RISC-V?)
Pin 67/68 UART RX/TX (DSP core UART?)
But Tristan document "rv_uart" UART mux pin missing? How to select RISC-V/DSP core UART? (might be pin 57 rx_ctl)
Boot from SD-card is possible:
https://www.vlsi.fi/fileadmin/news/PressReleaseVSRVES01.pdf
Yleisajattelija:
VSRV Device Tree:
https://www.vsdsp-forum.com/phpbb/viewtopic.php?t=3241
There is two UART connectors on board, so uart_mux pin is not needed (or it is automatically controlled):
https://www.vlsi.fi/en/support/evaluationboards/vsrves01catboard.html
Yleisajattelija:
I think Rasperry Pi DTO- type problems cannot be solved without physical memory managing system. If I understand correctly, it is optional feature on RISC-C processors:
https://github.com/ultraembedded/riscv/blob/master/doc/riscv_isa_spec.pdf
https://github.com/ultraembedded/riscv/blob/master/doc/riscv_privileged_spec.pdf
"An optional physical memory protection (PMP) unit provides per-hart machine-mode control registers to allow physical memory access privileges (read,write, execute) to be specified for each physical memory region."
Probably this "Flavour" switch "Smpmpmt" (= PMP-base memory types (for cores w/o MMU) (cacheable/uncacheable, idempotency, ordering) .
Not implemented on VSRV1 -board (yet).
I think this is very promising board for new Tinycore port. Very open source and very good documentation. It is RISC-V, and supported for scommunity. Company's business is to sell chips, and there is company strategy to support linux -ports:
---------------------------------------------------------------------
Resources
Below is a list of various free and open resources available now or soon from VLSI Solution. They will be updated regulardly as new information becomes available. Our goal is to in time provide
all information needed for our customers to compile and if necessary modify their own Linux kernels and applications.
Documentation:
VSRV Datasheet (NEW! 250507) - An extremely work-in-progress version at the moment
VSRV User's Guide (NEW! 250528) - What the VSRV chip and VSRVES01 Cat Board are and how to use them
VSRV VSOS Shell (NEW! 250530) - How to use the VSDSP VSOS Shell
VSRV VSOS Audio (NEW! 250617) - Introduction to the VSDSP VSOS audio subsystem
Software:
VSOS Root Image (NEW! 250604) - Latest version of the files for the VSRVES01 Cat Board's microSD card (including both VSDSP/VSOS and RISC-V/Linux)
elf2vri (NEW! 250618) - Linux C source code for program needed to convert Linux ELF and binary files to the VRI format required by CAT Board's DDRLoad
Other:
Linux Device Tree (NEW! 250602)
VSRVES01 discussion thread (NEW! 250508)
VSRVES01 Cat Board discussion thread (NEW! 250523)
-----------------------------------------------------------------------------------------
https://www.vlsi.fi/en/products/vsrves01.html
Navigation
[0] Message Index
[#] Next page
[*] Previous page
Go to full version