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Author Topic: RiscV  (Read 4135 times)

Offline limacon

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RiscV
« on: September 11, 2017, 07:31:39 AM »
Hey all.

I've been working on a custom RiscV Soc based on VexRisc - written in SpinalHDL (on top of scala).

newbielink:https://github.com/SpinalHDL/VexRiscv [nonactive]

Learn more about SpinalHDL here
newbielink:https://www.youtube.com/watch?v=dRhmH2eW7w4 [nonactive]

Long term goal is to boot Tiny Core. :-)
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Offline limacon

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Re: RiscV
« Reply #1 on: September 11, 2017, 07:32:21 AM »
Another RiscV SoC is the LowRisc project
newbielink:http://www.lowrisc.org/ [nonactive]
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